The invention relates to the general field of lateral diffused MOS (LDMOS) devices with particular reference to improving voltage breakdown without increasing on-resistance
An LDMOS device is basically a MOSFET fabricated using a double diffusion process with coplanar drain and source regions. A typical structure of the prior art is shown in FIG. 1. Nxe2x88x92 body of silicon 12 (that typically has a resistivity between about 0.1 and 1 ohm-cm) is isolated from Pxe2x88x92 substrate 11 by P+ boundaries 13. Pxe2x88x92 well 18 extends dohwnwards from the top surface and includes N+ source 17 whose distance L from the junction between 12 and 18 defines the channel. With the application of positive voltage VG to polysilicon gate 16 (beneath which is a layer of gate oxide not explicitly shown), current can flow through the channel from source 17 into Nxe2x88x92 body 12 to be collected at N+ drain 17.
Metal contact 15 shorts source 17 to P+ ohmic contact 19 and thence to substrate 12. This allows source current to be applied through the substrate which can then be cooled through a heat sink. The role of field oxide regions 14 is to release electric field crowding at poly edge of drain side.
The on-resistance of devices of this type is roughly proportional to their breakdown voltage because the value of the latter is determined by the resistivity of Nxe2x88x92 region 12. Thus, a compromise has to be made between minimum on-resistance and maximum breakdown voltage. Additionally, the higher the on-resistance the lower the high frequency cutoff of the device.
FIG. 2 is a plot of drain current vs. drain voltage in the off state for a device of the type illustrated in FIG. 1 This device had an on-resistance of around 1.1 mohm.cm2 and, as can be seen, breakdown has occurred at about 40 volts. The present invention discloses how the voltage breakdown of such a device may be raised by about 60% without having to increase the on-resistance.
A routine search of the prior art was performed with the following references of interest being found:
In U.S. Pat. No. 5,517,046, Hsing et al. disclose a DMOS device with a 2 step doping Nxe2x88x92 and N+ in an epi layer. As will become apparent, this invention teaches directly away from the present invention. Gregory, in U.S. Pat. No. 6,069,034, shows a DMOS with a buried drain that is connected to the surface through a sinker. U.S. Pat. No. 5,869,371 (Blanchard) discloses a VDMOS device similar to that of Hsing et al. U.S. Pat. No. 5,852,314 (Depetro et al.) and U.S. Pat. No. 5,48,147 (Mei) show related patents.
It has been an object of the present invention to provide an LDMOS device having significantly higher breakdown voltage, for the same on-resistance, than similar devices of the prior art.
This object has been achieved by having two epitaxial Nxe2x88x92 regions instead of the single epitaxial Nxe2x88x92 region that is used by devices of the prior art. The resistivities and thicknesses of these two Nxe2x88x92 regions are chosen so that their mean resistivity is similar to that of the aforementioned single Nxe2x88x92 layer. A key feature is that the lower Nxe2x88x92 layer (i.e. the one closest to the Pxe2x88x92 substrate) has a resistivity that is greater than that of the upper Nlayer. If these constraints are met, as described in greater detail in the specification, improvements in breakdown voltage of up to 60% can be achieved without having to increase the on-resistance.